1. Field of the Invention
The present invention relates generally to a hardware/software construct which converts data flow on one medium to data flow compatible to another medium. More specifically, the generic high bandwidth adapter of the present invention provides a data interface between system buses, switching fabrics, transmission media, and a variety of Local Area Networks (LANs).
2. Discussion of the Prior Art
In the prior art, communication adapter technology has enjoyed a speed advantage over available transmission technology. Recent advances in transmission technology have broken this balance, leaving the communicator with excessive capabilities. With communication rates approaching or exceeding computation rates, it has been necessary to explore alternate communication architectures. This exploration has concentrated on the two areas of new protocols and optimal implementation of existing protocols.
The progress in transmission technology has provided not only much higher data rates but also much lower error rates. Existing communication protocols were designed assuming high media error rates and data rates much lower than computational speed. An enormous emphasis was placed on providing error recovery capability to avoid excessive use of the slow transmission media. As the basic assumptions have become progressively less true, existing communication protocols have become increasingly unsuitable for new transmission media. Another contribution to the mismatch of transmission capabilities and protocols comes from the fact that many existing communication protocols were designed for "general purpose processor/software" implementations. The "software oriented" design approach of these protocols has made communication protocol processors the bottleneck in data transmission.
To correct these known design deficiencies in existing communication protocols, several new fast lightweight protocols have been proposed. Compared with existing communication protocols, these protocols emphasize high data throughput and de-emphasize complicated error recovery schemes. In addition, most of these new lightweight protocols are designed with VLSI hardware implementations in mind.
In addition to the design deficiencies mentioned above, the data throughput of existing communication protocols is further hampered by another deficiency in many current protocol implementations. This implementation deficiency is the worst case (or penalize everyone) design principle, which specifies that all packets are to be treated equally. This treatment is without regard to the behavior of the packet. A packet which is in sequence and without error traverses much the same software path as the out-of-sequence or corrupted packet. This design principle was justified in a low transmission rate, lossy network, due to high error rates and minimal impact of software path lengths on communication latency. However, with the very low error rates of current transmission technologies, the probability of good-behavior packets is significantly increased and the potential packet arrival rate is greatly increased. Protocol implementations must be adjusted accordingly.
The activities in this area have been mainly the modification of current protocol implementations, rewarding good-behavior packets and penalizing only the bad-behavior packets. Implementation schemes have also included the pipelining of packet operations and hardware functional assists.
This throughput problem becomes even more complicated for a high-speed communication adapter due to the following additional constraints:
Compatibility with Existing Protocols & Implementations. PA1 A high-speed communication adapter is expected to support new communication technologies and provide downward compatibility to existing communication technologies. Downward compatibility means not only supporting existing communication protocols, but also possibly supporting the methods or architectures with which existing protocols have been implemented. PA1 Compatibility with Established System Buses and/or Channels. PA1 More often than not, a communication adapter will act as a communication front-end for a host system. That means that most of the adapter packet data will either come from or go to an attached host system through an established system bus or I/O channel. From the point of view of end-to-end performance, the data transfer between an adapter and its attached host system is as important as, if not more important than, any other segment of the communication path between two end-nodes. A high-speed communication adapter is expected to support high data transfers on a family of long-established system buses and I/O channels and still be able to abide by the architectural rules of those buses and channels. PA1 Provision for the high speed transport of packets into, through, and out of the generic high bandwidth adapter. PA1 Hardware assist for buffer and queue management and data movement. PA1 Support for multiple priority levels and types of services. PA1 Provision of a uniform buffer/packet/queue/server management scheme over a wide range of bus and transmission technologies. PA1 The support of high sustained throughput. PA1 Possibility of very low host load for communications due to the provision of a high level software interface. PA1 The support of multiple concurrent protocol stacks. PA1 Provision for fast prototyping of new packet-based transmission technologies. PA1 Micro Channel 800 Mbps (Streaming Mode) PA1 Cross Bar Switch--Very Low Latency 240 Mbps/port. PA1 Serial I/O Channel 200 Mbps. PA1 SPD Bus 80 Mbps. PA1 370 Channel OEMI 24 Mbps. PA1 Hardware Data Link Control 400 Mbps. PA1 FDDI--ANSI Standard Fiber Token Ring 100 Mbps. PA1 DS3 (Clear Channel T3) 45 Mbps. PA1 Token King 16/4 Mbps. PA1 Ethernet 10 Mbps. PA1 APPN/SNA. PA1 APPC. PA1 TCP/IP. PA1 ISO/TP & ISO/IP. PA1 Broadband ISDN. PA1 Portions of VTAM Support.